The present invention relates in general to memory devices, and, in particular, to an interleaved memory readable in a synchronous mode by successive locations with a sequential type of access commonly referred to as burst mode, and to a standard memory read in a random access asynchronous mode with fast access times.
In a standard memory a read cycle is defined from a request of data effected by way of the input of a new address to the final output of the bits stored in the addressed location (byte, word, etc.). Internally, the reading process evolves through several steps. These steps include the acquisition of the new address to their decoding, to the generation of synchronizing pulses of the sensing circuits, to the output of the read data, and the like. The fundamental steps of a read cycle and the typical control signals that are used for managing it are depicted in FIG. 1.
The ATD (Address Transition Detection) signal recognizes a change of the address input by the external circuitry and, therefore, the new access request initiates a new read cycle. After enabling the sense amplifiers by way of the signal SAenable, an equalization of the sensing circuitry takes place at the end of which, as timed by the signal EQZ, the effective reading of the memory cells takes place. Finally, after a certain interval of time that may vary from device to device, by way of a signal SAlatch, the recording of the read data into the latches in cascade to the sense amplifiers takes place. This is from where the read word may be transferred to the output buffers.
In memory devices designed for a synchronous read mode with a sequential type (burst) of access, the reading process exploits the fact that the reading takes place by successive locations. That is, the subsequent memory location to be read and, therefore, its address is predictable from the address of the location being currently read. A subgroup of these sequential (burst) synchronous read mode memories is represented by the so-called interleaved memories. A burst access interleaved memory is described in U.S. Pat. No. 5,559,990, for example.
In this type of memory, the cell array is divided in two semi-arrays or banks, each having its own read circuitry. The read streams of the two banks are thereafter superimposed though, according to one of the most commonly followed approaches. They are outphased from each other, while on one of the two banks or semi-arrays the steps of evaluation and transfer of the data to the output are being performed. On the other bank or semi-array (the next location to be addressed) a new read cycle may be started without waiting for the conclusion of the current read cycle that involves the first semi-array.
In interleaved memories, a basic scheme of which is depicted in FIG. 2, the array is divided in two independent banks or semi-arrays, EVEN and ODD, respectively, each having its own independent read path. Typically, there are two counters, one for each bank, containing the address of the currently pointed memory location. In case of simultaneous reading processes evolving respectively on the two semi-arrays, the least significant bit of the address (A0) supports the multiplexing between the EVEN and the ODD banks. If A0=0, the data coming from the EVEN semi-array will be made available at the output. If A0=1, the data coming from the ODD semi-array will be made available at the output.
As it is commonly known, the reading of the two semi-arrays is carried out according to one of two different approaches: simultaneous readings and multiplexing of the outputs; or time outphased readings.
According to the first approach, the readings are simultaneous on the two banks. The data read are stored in respective output registers and made available to the outside world in synch with an external clock signal. According to the second approach, the readings on the two semi-arrays have an alternate and interleaved evolution on a time base.
The first approach, though offering a simpler hardware implementation, limits the minimization of the start times of synchronous read cycles. For a better comprehension, it is necessary to consider the basic steps that are performed when passing from an asynchronous read mode to a synchronous read mode. With reference to the scheme of FIG. 2, and supposing a start of the reading from an address X, the latter will be loaded on the EVEN bank counter and on the ODD bank counter, less the least significant bit (A0) of the address. The two counters will point to the same location X of the respective bank or semi-array.
If A0=0: the first read data is relative to the address X of the bank EVEN and the successive read data is the data X of the bank ODD.
If A0=1: the first read data is relative to the address X of the bank ODD and the successively read data is relative to the X+1 address of the bank EVEN.
In the first case, it is sufficient to perform a simultaneous reading of the two banks and multiplex the outputs. In the second instance, it is necessary to increment the counter before starting the reading on the bank EVEN.
Usually, known synchronous memory devices do not make any initial increment and wait for the successive cycle for incrementing both counters, and therefore, read the location X+1 of the banks EVEN and ODD. This makes the times of the first read cycle and of the second sequential read cycle at best equal to the asynchronous read mode time of the memory.
In general, it may be stated that the efficient management of the read processes has a direct influence of the performance of the memory device. Many read path architectures have been proposed. Known read path architectures have generally been conceived for responding efficiently to either one or the other of the two modes of operation: asynchronous or synchronous.
If a memory device is designed to be read in an asynchronous mode, it will be generally provided with a rather simple control circuitry of the read data streams. This allows for the use of adaptive structures, such as dummy wordlines and dummy sense amplifiers, while leaving the reading circuitry free to evolve as fast as possible to achieve the shortest asynchronous access delays.
In contrast, in memory devices designed to function in a burst access mode or in a synchronous read mode, the possibility of making available in output a certain number of words read and stored in advance, permits, after a first asynchronous access, as long as it may be, a series of extremely fast read cycles. In this case though, the control logic must intervene heavily to manage the sense amplifiers which should not be left to evolve freely but be enabled, equalized and read at precise instants established by the control system. Prior European Patent Application Serial No. EP-98830801, filed on Dec. 30, 1998, and Italian Patent Application Serial No. MI99A00248, filed on Nov. 26, 1999, describe burst mode EPROM devices with the above characteristics. These patent applications are both incorporated herein by reference in their entirety, and are assigned to the assignee of the present invention.
An object of the present invention is provide a multipurpose memory device that can be used in a broader range of applications, whether requiring the reading of data from the memory in an asynchronous mode with random access (as in a standard memory) or the reading of data from the memory in a synchronous mode with sequential or burst type access. The multipurpose memory device should be capable of recognizing the mode of access and the reading that is currently required by the microprocessor. The multipurpose memory device should also self-condition its internal control circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time of data compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.
This and other objects, features and advantages in accordance with the present invention are provided by a memory architecture, according to which two totally independent and uncorrelated read paths of data stored in the two semi-arrays of an interleaved memory (named EVEN and ODD) are established. These independent and uncorrelated read paths are provided while making compatible the functioning of the memory device according to an asynchronous mode of one and/or of the other semi-array by using a special generator of ATD signals (Address Transition Detector) that may be stimulated by events different from transitions in the input circuitry of acquisition of the addresses from outside. In addition, the requested mode to the control circuit is rendered recognizable to the memory by way of a specific protocol using two of the commonly used external commands, namely the address latch enabling signal ALE and the read stimulation signal RD.
The counters of the two semi-arrays or banks or, according to a preferred embodiment, the counter of the first bank and a more simpler register with functions of an address counter for the second bank, are incremented distinctly from one another, and are thus outphased from the reading on the two banks already from the first (asynchronous) read cycle. This is different from what is commonly done in interleaved memory devices. Therefore, the memory device of the invention is perfectly able to switch to a synchronous mode reading phase at any time, while practically halving the access time to such a mode.
The two different reading processes, according to an asynchronous random access mode and according to a synchronous burst access mode remain perfectly congruent with each other and have an alternate and interleaved evolution in time. The architecture of the invention provides for optimal performances, uncompromised in any measure by the bivalent character of the device, whether commanded to function as a standard asynchronous random access memory or as a synchronous burst access memory.
The control circuit of the memory recognizes the type of access and reading mode that is required by way of a specific protocol of use of two external commands, namely the ALE and RD signals. The start of a standard read cycle (asynchronous mode) takes place as customary when the ALE signal assumes a high logic level 1. Upon the switching to a logic 1 of the ALE signal, the memory acquires (in its input latches) the desired address and simultaneously starts up the sense circuitry of both banks. Of course, a first cycle will always be asynchronous and the independent arrays of sense amplifiers of the two banks are simultaneously activated.
If the ALE signal does not return to its rest condition, that is to a logic 0 state, the two banks of sense amplifiers will complete their respective readings. Each reading evolves according to its own self-adapting circuits, in the same manner as it occurs in a standard asynchronous memory. At the end of these readings, only the bank currently in a condition of priority, determined by the value of the least significant bit of the address, will be enabled to place the read data on an internal data bus: with ADD less than 0 greater than =0 establishing the priority of the EVEN bank and ADD less than 0 greater than =1 establishing the priority of the ODD bank.
Under these conditions, the reading stimulation signal RD behaves as an active low Output Enable command, such that when at a logic 0 level, the data of the bank currently in priority is transferred to the output buffers and therefore made available to the external world. If, during the very first read cycle or thereafter during the nth asynchronous random access read cycle, the ALE signal switches back to a logic 0 level, the control circuit interprets such an occurrence as a request for a change to a burst mode of access and to a synchronous read mode of the memory.
In such a case, the control circuit generates a first increment pulse for the address counter (or optionally for the functionally equivalent register) of the bank which currently is not in priority. In so doing, the reading of the data on the bank currently in priority is left to evolve, considering that this bank will be the first to be called to provide its data to the output of the memory. Simultaneously the incremented address for the successive reading to be done on the other bank is prearranged (start of the synchronous burst interleaved reading mode).
According to an important aspect of the architecture, the same increment pulse for the address counter (or register) of the bank currently not in priority, stimulates also the respective reading circuitry of the bank. A specially modified ATD generator generates upon stimulation by the address counter incrementing pulses, including a dummy ATD pulse that is due to internal stimulation and which is exclusively conveyed to the bank not in priority and to its decoding and sensing circuits.
In this way, the array of sense amplifiers of the bank not in priority, the relative sense control circuit and equalization dummy structures, etc., will interpret the address counter incrementing pulse as a normal asynchronous read cycle request and will restart. This is while the sense amplifiers of the bank currently in priority, being completely independent from those of the other bank, will continue to evolve in their reading process.
The control circuit of the memory will continue to monitor the signals coming from the sense control of the bank in priority. As soon as the sense control circuit provides the SAlatch signal for transferring the read data to the latches immediately in cascade of the respective sense amplifiers, the control circuit will generate a pulse commanding the loading of data on the output, i.e., a LOAD pulse. In this way, the functioning enters in a burst interleaved access mode.
The end of the LOAD pulse establishes the availability of the bank that has just terminated a read cycle to start a new read cycle. Therefore, a new address counter incrementing signal will be generated only for the counter (or equivalent register) of such a bank. Beside stimulating the generation of a sequentially updated internal address, this will cause the generation of a new ATD pulse by internal stimulation (dummy) exclusively conveyed to the circuitry of such a bank.
These succession of address counter incrementing pulses have also the function of commuting the priority between the two banks in an alternate manner. In fact, because the first bank has terminated a read cycle and is about to start a new one, the bank that was not in a priority state and that in the meanwhile had restarted on its up-dated address, assumes priority.
Therefore, the control circuit of the memory will again wait for information coming from the asynchronous and self-adapting structures of sense control of such a bank as well as for an authorization by way of the external command RD to place in output the data of such a bank, by way of the generation of a new LOAD pulse. From hereon, the steps described above may repeat indefinitely, alternating the sequence.
According to a preferred embodiment, the circuit that detects transitions in the latches acquiring the externally requested addresses generates a detection signal ATD even upon a switching of the outputs. This is during a phase of reentering from a state of stand-by with the external command ALE=0, besides the acquisition of a new address from outside during a phase of random access, or upon the incrementing of one or of the other address counter of the two banks during a phase of sequential access. This provides for a useful resume and recovery functionality such to produce in output the last read data before entering the phase of stand-by or the data relative to the sequentially successive address, depending on the logic state of the RD command at the moment of interrupting the sequential reading and entering in a phase of stand-by of the memory.
According to another preferred embodiment, the memory comprises a special circuit for discriminating the impulses of the external command ALE intended for the memory from those intended to other devices of the system, coordinately with an enabling command of the memory device CEn that commonly filters the ALE command.
According to yet another preferred embodiment, the memory comprises a special circuit for accelerating the carry generation in the address counters of the two banks of the memory.
According to a further embodiment, the memory comprises a special circuit for generating synchronization signals on the basis of external commands and of internally generated signals in order to optimize the management of certain circuits that are shared by both banks of the memory.